Skip navigation
Please use this identifier to cite or link to this item: http://dx.doi.org/10.25673/13478
Title: Hardware Implementation of IP Packet Filtering in FPGA
Author(s): Cholakoska, Ana
Efnusheva, Danijela
Kalendar, Marija
Issue Date: 2019-03-06
Language: English
Subjects: FPGA
IP Header Fields Extracting
IP Packet Filtering,
Network IDS Systems
Abstract: In the present rapid expansion of the number of computers and devices connected to the Internet, one of the top three issues that need to be addressed is the network security. The greater the number of connected users and devices, the attempts to invade privacy and data of connected users becomes more and more tempting to hostile users. Thus, network intrusion detection systems become more and more necessary and present in any network enabling Internet connections. This paper addresses the network security issues by implementing NIDS style hardware implementation for filtering network packets intended for faster packet processing and filtering. The hardware is based on several NIDS rules that can be programmed in the system's memory, thus enabling modularity and flexibility. The designed hardware modules are described in VHDL and implemented in a Virtex7 VC709 FPGA board. The results are discussed and analyzed in the paper and are presenting good foundation for further improvement.
URI: https://opendata.uni-halle.de//handle/1981185920/13565
http://dx.doi.org/10.25673/13478
Open access: Open access publication
Appears in Collections:International Conference on Applied Innovations in IT (ICAIIT)

Files in This Item:
File Description SizeFormat 
1_5_Cholakoska.pdf566.21 kBAdobe PDFThumbnail
View/Open
Show full item record BibTeX EndNote


This item is licensed under a Creative Commons License Creative Commons