Please use this identifier to cite or link to this item:
http://dx.doi.org/10.25673/5882| Title: | FPGA Implementation of IP Packet Header Parsing Hardware |
| Author(s): | Efnusheva, Danijela Tentov, Aristotel Cholakoska, Ana Kalendar, Marija |
| Editors: | Siemens, Eduard Krause, Bernd Mylnikov, Leonid |
| Type: | Hochschulschrift |
| Type: | Book |
| Language: | English |
| Publisher: | Bibliothek, Hochschule Anhalt |
| URN: | urn:nbn:de:gbv:kt1-2578 |
| URI: | https://opendata.uni-halle.de//handle/1981185920/12693 http://dx.doi.org/10.25673/5882 |
| Open Access: |  Open access publication |
| Appears in Collections: | Elektrotechnik, Maschinenbau und Wirtschaftsingenieurwesen |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| ICAIIT V 1_05 Efnusheva_Tentov_Cholakoska_Kalendar.pdf | 399.92 kB | Adobe PDF |  View/Open |