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Please use this identifier to cite or link to this item: http://dx.doi.org/10.25673/5882
Title: FPGA Implementation of IP Packet Header Parsing Hardware
Author(s): Efnusheva, Danijela
Tentov, Aristotel
Cholakoska, Ana
Kalendar, Marija
Type: Hochschulschrift
Publisher: Bibliothek, Hochschule Anhalt
URN: urn:nbn:de:gbv:kt1-2578
URI: https://opendata.uni-halle.de//handle/1981185920/12693
http://dx.doi.org/10.25673/5882
Open access: Open access publication
Appears in Collections:Elektrotechnik, Maschinenbau und Wirtschaftsingenieurwesen

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